The present invention generally relates to a voltage generator and, more particularly, to a voltage generator for a semiconductor device such as a semiconductor memory device.
FIG. 1 shows an arrangement of a sense amplifier circuit 1 for amplifying a potential difference on bit lines BL and /BL. Memory cells (not shown) such as dynamic random access memory (DRAM) cells are connected to the bit lines. Sense amplifier circuit 1 includes P-channel MOS transistors 2 and 3 and N-channel MOS transistors 4 and 5. P-channel MOS transistor 2 has a gate connected to bit line /BL and a first end connected to bit line BL. P-channel MOS transistor 3 has a gate connected to bit line BL and a first end connected to bit line /BL. The second ends of P-channel MOS transistors 2 and 3 are connected together to a drive signal line 7 which is selectively supplied with a sense amplifier drive signal SAP. N-channel MOS transistor 4 has a gate connected to bit line /BL and a first end connected to bit line BL. N-channel MOS transistor 5 has a gate connected to bit line BL and a first end connected to bit line /BL. The second ends of N-channel MOS transistors 4 and 5 are connected to a drive signal line 8 which is selectively supplied with a sense amplifier drive signal /SAN. FIG. 1 further shows a PMOS driver transistor 6 having a first end connected to drive signal line 7 and a second end connected to a VBLH generator. The gate of PMOS driver transistor 6 is supplied with a switching signal for turning ON PMOS driver transistor 6 to supply the sense amplifier drive signal SAP to the second ends of P-channel MOS transistors 2 and 3.
FIG. 2 shows a conventional PMOS voltage generator 10, which may be used as the VBLH generator of FIG. 1. PMOS voltage generator 10 includes a comparator 12, a P-channel MOS transistor 14, a first resistive element 16, and a second resistive element 18. P-channel MOS transistor 14, resistive element 16, and resistive element 18 are connected in series between a first voltage VCC (e.g., 3.3 volts) and a second voltage VSS (e.g., ground). The output terminal of PMOS voltage generator 10 is a node between P-channel MOS transistor 14 and resistive element 16. The output voltage VBLH may be, for example, 1.8 volts. One input terminal of comparator 12 is connected to a reference voltage and the other input terminal of comparator 12 is connected to a feedback voltage derived from a node between first and second resistive elements 16 and 18.
However, the feedback operation of PMOS voltage generator 10 of FIG. 2 is relatively slow and it is difficult for PMOS voltage generator 10 to satisfy peak current demands. In order to overcome this problem, a so-called xe2x80x9cactive-kickerxe2x80x9d may be provided as shown in FIG. 3. Specifically, the active kicker is a P-channel MOS transistor 20 connected between the voltage VCC, illustrated in the figure as being set at 3.3V, and the output terminal of the PMOS voltage generator 10. This active kicker is switched ON to provide a larger current IBLH and thereby enhance the response of the voltage generator. However, the active kicker causes noise problems. In addition, since the current IBLH depends on various factors such as the data pattern of the data stored in the memory cells to which the bit lines are connected, the memory cell capacitance, and the bit line capacitance, it is difficult to provide the appropriate current IBLH.
FIG. 4 shows a conventional NMOS source follower type voltage generator 40. Voltage generator 40 includes a VppA generator 32 and an N-channel MOS driver transistor 34. Examples of circuits which may be utilized as VppA generator 32 are shown in FIGS. 5(a) and 5(b). N-channel MOS driver transistor 34 has a first end connected to a voltage VCC (e.g., 3.3 volts) and a gate supplied with the output voltage of VppA generator 32 (e.g., about 2.3 volts). N-channel MOS driver transistor 34 is a relatively large transistor having, for example, a total channel width of about 74 millimeters and a channel length of about 0.36 micrometers. A VBLH voltage of 1.8 volts is output from voltage generator 40. Voltage generator 40 of FIG. 4 is advantageous in that it is responsive to rapid variations of load current. However, as can be seen with reference to FIG. 7(a), the sub-threshold current of the N-channel MOS driver transistor 34 gradually raises the output voltage VBLH during a pre-charge cycle (including a stand-by condition) and a low-frequency operation condition. VppA may be a constant voltage (for example, 2.3 V). Accordingly, the gate voltage of the N-MOS driver 34 is also kept constant. When the voltage difference between the gate node of the NMOS driver and the source node of the NMOS driver becomes larger than the threshold voltage of the NMOS driver, large current is supplied to the VBLH node. When the load current becomes, zero, the sub-threshold leakage of the NMOS driver causes xe2x80x9cvoltage creep.xe2x80x9d The degree of voltage creep depends on the characteristics of the N-channel MOS driver transistor, but such creep could adversely affect restore levels or sensing margin.
One solution to this voltage creep is to utilize a current bleeder circuit 36 as shown in FIG. 6. Bleeder circuit 36 bleeds the sub-threshold current of the N-channel MOS driver transistor 34 so that voltage creep may be eliminated as can be seen with reference to FIG. 7(b). In general, subthreshold leakage does not depend on the active/stand-by state of the device. To suppress the voltage creep completely, a large bleeder current is needed even when the device is in a stand-by state. However, a bleeder circuit wastes current. For example, the bleeder currents in the active and stand-by states are 2 milliamps and 1 microamp, respectively, in for example a 64 Mbit DRAM. If the size of the NMOS driver transistor is increased to provide for a larger current IBLH and to thereby improve response, the bleeder current becomes even larger. In the case of a 256 Mbit DRAM, the size of the NMOS driver transistor becomes four times larger than that of the 64 Mbit DRAM. So the resulting bleeder current becomes four times larger than that found in the 64 Mbit DRAM. In addition, if the actual sub-threshold leakage current is different from the design value (due to, for example, process variations), current compensation can become difficult and the characteristics of VBLH may be adversely affected.
Because of the connection to the bit lines, the IBLH can be a very large and spiky current, particularly in the case of highly integrated semiconductor memory devices such as 256 Mbit DRAM devices. Accordingly, the construction and operation of the VBLH generator is a very important design consideration for highly integrated semiconductor memory devices. While the above-described arrangements might be effectively adapted for use in semiconductor memory devices such as 16 Mbit DRAMs, the current requirements for highly integrated semiconductor memory devices such as 256 Mbit DRAMs make use of VBLH generators such as those described above problematic.
In addition, the type and layout of the components of the VBLH generator can adversely impact on the goal of achieving a highly integrated memory device. For example, the N-channel MOS driver transistors of the VBLH generators have been arranged adjacent to a memory cell array as shown in FIG. 8. FIG. 8 shows a memory cell array 90. Although not shown in FIG. 8 for purposes of clarity, memory cell array 90 includes DRAM cells arranged in rows and columns and connected to word lines and bit lines. VBLH driver component sections 92a and 92b are arranged on two opposite sited of memory cell array 90. Each of these sections 92a and 92b is connected to VBLH wire 94 which extends above the memory cell array 90. In the arrangement of FIG. 8, separate relatively wide power lines are required for supplying power to each of the sections 92a and 92b. This can complicate the arrangement of wiring connections between the memory cell array 90 and the column decoder and DQ buffer section 94.
In accordance with one aspect of the present invention, a voltage generator for outputting an output voltage at an output terminal thereof includes a driver MOS transistor of a first conductivity type having a first end connected to said output terminal and a capacitor connected between the output terminal and a second voltage node. The capacitor comprises a plurality of trench capacitors formed in a semiconductor substrate.
The use of trench capacitors for the capacitor is advantageous as compared, for example, with the use of planar capacitors because trench capacitors can provide a high capacitance while using a relatively small amount of area. Thus, the use of trench capacitors is consistent with the goal of providing highly integrated semiconductor memory devices. In addition, the structure of trench capacitors used for the capacitor is preferably almost the same as the capacitor of a memory cell. Thus, the trench capacitors for the capacitor can be formed without significant impacting the semiconductor memory device manufacturing process.
In accordance with another aspect of the present invention, a semiconductor memory device includes a plurality of memory cell arrays, each memory cell array comprising memory cells connected to bit lines and sense amplifiers for sensing potential differences on the bit lines. Voltage generators generate voltages supplied to the sense amplifiers, wherein each voltage generator includes driving circuitry arranged on one side of a corresponding one of the memory cell arrays and capacitors arranged on a side of the corresponding one of the arrays opposite to the one side.
By forming the capacitors on a side of the memory cell array opposite to the driving circuitry, the capacitors can thereby function as a passive current supply. In addition, since the driver circuitry is located on only one side of the array, a power line for the voltage generator need only be provided on one side of the array, thereby simplifying wiring.